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    • 专利摘要:
    An optoelectronic device (10) includes a first optoelectronic circuit (12) attached to a second electronic circuit (14). The second electronic circuit (14) comprises conductive pads (62). The first optoelectronic circuit comprises, for each pixel: at least first and second three-dimensional semiconductor elements (20, 22) extending over a first conductive layer and having the same height (H); first active areas based on the first semiconductor elements and adapted to emit or pick up a first electromagnetic radiation; second active regions resting on the second semiconductor elements and adapted to emit or pick up a second electromagnetic radiation; and second, third and fourth conductive layers (42, 44, 48) electrically connected to the conductive pads (62), the second, third and fourth conductive layers being respectively connected to the first active areas, the second active areas and the first layer. conductive.
    公开号:FR3068517A1
    申请号:FR1756161
    申请日:2017-06-30
    公开日:2019-01-04
    发明作者:Eric Pourquier
    申请人:Aledia；
    IPC主号:
    专利说明:

    OPTOELECTRONIC DEVICE COMPRISING THREE-DIMENSIONAL SEMICONDUCTOR STRUCTURES IN AXIAL CONFIGURATION
    Field
    The present invention relates generally to optoelectronic devices comprising three-dimensional semiconductor elements of the nanowire or microfilm type, and their manufacturing process, and more particularly to optoelectronic devices suitable for displaying images, in particular a display screen or a projection device. images.
    Presentation of the prior art
    A pixel of an image corresponds to the unitary element of the image displayed or captured by the optoelectronic device. For the display of color images, the optoelectronic device generally comprises, for the display of each pixel of the image, at least three components, also called display sub-pixels, which each emit light radiation substantially in only one color (for example, red, green and blue). The superposition of the radiations emitted by these three display sub-pixels provides the observer with the colored sensation corresponding to the pixel of the displayed image. In this case, the display pixel of the optoelectronic device is called
    B16168 - Small pix the set formed by the three display sub-pixels used for displaying a pixel of an image.
    There are optoelectronic devices comprising three-dimensional semiconductor elements of the nanowire or microfilm type allowing the production of so-called three-dimensional light-emitting diodes. A light emitting diode includes an active area which is the region of the light emitting diode from which most of the electromagnetic radiation supplied by the light emitting diode is emitted. A three-dimensional light-emitting diode can be produced in a so-called radial configuration, also called core / shell, in which the active zone is formed at the periphery of the three-dimensional semiconductor element. It can also be produced in a so-called axial configuration, in which the active zone does not cover the periphery of the three-dimensional semiconductor element but extends essentially along a longitudinal axis of epitaxial growth.
    Three-dimensional light-emitting diodes in an axial configuration have a lower emitting surface than light-emitting diodes in a radial configuration, but have the advantage of being made of a semiconductor material of better crystalline quality, thus offering a higher internal quantum efficiency, in particular a better relaxation of the stresses at the interfaces between the semiconductor layers. In the case of quantum wells produced in InGaN, the three-dimensional light-emitting diodes in axial configuration thus make it possible to incorporate more indium to emit, for example, in red or green.
    There is a need to produce an optoelectronic device whose display pixels have a reduced lateral dimension, in particular less than 5 μm. However, the production of such an optoelectronic device with three-dimensional light-emitting diodes in an axial configuration can be difficult. In addition, it would be desirable for the
    B16168 - Small pix method of manufacturing the optoelectronic device comprises as many common steps as possible with a method of manufacturing an optoelectronic device comprising planar electroluminescent in which the areas of the light emitting diodes are formed on planes.
    summary
    Thus, an object of at least in part the three-dimensional optoelectronics active diodes layers to overcome the disadvantages of light emitting devices embodiment is of diodes described above, object of a light emitting diodes
    Another three-dimensional embodiment is that are in the axial configuration.
    Another object with a lateral dimensions of the optoelectronic pixels are less than 4 µm.
    Another object of a mode of the manufacturing process steps after the compatible manufacturing circuits of the diode embodiments is that of display of the device at 5 pm, preferably of realization that the light-emitting optoelectronic devices are of manufacturing CMOS transistors realization provides a device with integrated processes.
    Thus, an optoelectronic mode comprising a first optoelectronic circuit attached to a second electronic circuit, the second electronic circuit comprising electrically conductive pads, the first optoelectronic circuit comprising pixels and comprising, for each pixel:
    a first electrically conductive layer;
    at least first and second three-dimensional semiconductor elements extending perpendicular to the first electrically conductive layer and in contact with the first electrically conductive layer and having the same
    B16168 - Small pix height measured perpendicular to the first electrically conductive layer;
    first active areas resting on the ends of the first three-dimensional semiconductor elements opposite the first electrically conductive layer and adapted to emit or pick up a first electromagnetic radiation at a first wavelength;
    second active zones resting on the ends of the second three-dimensional semiconductor elements opposite to the first electrically conductive layer and adapted to emit or pick up a second electromagnetic radiation at a second wavelength different from the first wavelength; and second, third and fourth electrically conductive layers electrically connected to the electrically conductive pads, the second electrically conductive layer being connected to the first active areas, the third electrically conductive layer being connected to the second active areas and the fourth electrically conductive layer being connected to the first electrically conductive layer.
    According to one embodiment, the diameter of each first semiconductor element in contact with the first electrically conductive layer is less than the diameter of each second semiconductor element in contact with the first electrically conductive layer.
    According to one embodiment, the first three-dimensional semiconductor elements are regularly distributed according to a first average pitch and the second three-dimensional semiconductor elements are regularly distributed according to a second average pitch different from the first average pitch.
    According to one embodiment, the first optoelectronic circuit further comprises, for each pixel:
    at least third three-dimensional semiconductor elements extending perpendicular to the first
    B16168 - Small pix electrically conductive layer and in contact with the first electrically conductive layer, the first, second and third three-dimensional semiconductor elements having the same height measured perpendicular to the first electrically conductive layer;
    third active zones resting on the ends of the third three-dimensional semiconductor elements opposite to the first electrically conductive layer and adapted to emit or pick up electromagnetic radiation at a third wavelength different from the first and second wavelengths; and a fifth electrically conductive layer electrically connected to one of the electrically conductive pads and connected to the third active zones.
    According to one embodiment, the diameter of each second semiconductor element in contact with the first electrically conductive layer is less than the diameter of each third semiconductor element in contact with the first electrically conductive layer.
    According to one embodiment, the third three-dimensional semiconductor elements are regularly distributed according to a third average pitch different from the first average pitch and the second average pitch.
    According to one embodiment, the first and second active zones comprise a single quantum well or multiple quantum wells.
    According to one embodiment, the first and second three-dimensional semiconductor elements are mainly made of a semiconductor material chosen from the group comprising compounds III-V, compounds II-VI or semiconductors or compounds of group IV.
    According to one embodiment, the first and second three-dimensional semiconductor elements are of wire, conical or frustoconical shape.
    B16168 - Small pix
    According to one embodiment, the maximum dimension of each pixel measured parallel to the first electrically conductive layer is less than 5 μm.
    An embodiment also provides for a method of manufacturing the optoelectronic device as defined above, comprising the following successive steps:
    a) forming the first optoelectronic circuit; and
    b) fixing the first optoelectronic circuit to a second electronic circuit by electrically connecting the second, third and fourth electrically conductive layers to the electrically conductive pads.
    According to one embodiment, step a) comprises the following successive steps:
    c) simultaneously forming on a support the first and second three-dimensional semiconductor elements;
    d) simultaneously forming the first active areas on the ends of the first three-dimensional semiconductor elements opposite the support and the second active areas on the ends of the second three-dimensional semiconductor elements opposite the support;
    e) forming the second, third and fourth electrically conductive layers;
    f) remove the support; and
    g) forming the first electrically conductive layer.
    According to one embodiment, step a) comprises the following steps between steps c) and d):
    h) forming an electrically insulating layer between the first three-dimensional semiconductor elements and between the second three-dimensional semiconductor elements;
    i) partially etching the electrically insulating layer and the first and second three-dimensional semiconductor elements so that the first and second three-dimensional semiconductor elements have the same height.
    B16168 - Small pix
    According to one embodiment, the method further comprises, between steps f) and g), the step of etching the electrically insulating layer and the first and second three-dimensional semiconductor elements on the side opposite to the first and second active areas.
    Brief description of the drawings
    These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments made without implied limitation in relation to the attached figures, among which:
    Figure 1 is a sectional view, partial and schematic, of an embodiment of an optoelectronic device with microfibers or nanowires;
    Figure 2 is a detail view of part of Figure 1;
    Figures 3 to 7 are views similar to Figure 2 of other embodiments of the optoelectronic device; and FIGS. 8A to 8Q are partial and diagrammatic sections of structures obtained at successive stages of an embodiment of a method of manufacturing the optoelectronic device of FIG. 1.
    detailed description
    For the sake of clarity, the same elements have been designated by the same references in the different figures and, moreover, as is usual in the representation of electronic circuits, the various figures are not drawn to scale. In addition, only the elements useful for understanding this description have been shown and are described. In particular, the means for controlling the light-emitting diodes of the optoelectronic device are well known and are not described.
    In the following description, when reference is made to qualifiers of relative position, such as the terms above, below, upper, lower, etc., reference is made to the orientation of the figures or to a device
    B16168 - Small optoelectronic pix in a normal position of use. Unless otherwise indicated, the terms substantially, approximately, approximately and of the order of mean to the nearest 10%, preferably to the nearest 5%.
    The present application relates in particular to optoelectronic devices comprising three-dimensional elements, for example microfils, nanowires, conical elements or frustoconical elements. In particular, a conical or frustoconical element can be a conical or frustoconical element of revolution or a conical or frustoconical pyramid element. In the following description, embodiments are described in particular for optoelectronic devices with microfibers or nanowires. However, these embodiments can be implemented for three-dimensional elements other than microfibers or nanowires, for example conical or frustoconical three-dimensional elements.
    The term microfil, nanowire, conical element or frustoconical element designates a three-dimensional structure of elongated shape in a preferred direction of which at least two dimensions, called minor dimensions, are between 5 nm and 2.5 pm, preferably between 50 nm and 1 pm, the third dimension, called the major dimension, being greater than or equal to 1 time, preferably greater than or equal to 5 times, the largest of the minor dimensions.
    In the following description, the term yarn is used to mean microfil or nanowire. Preferably, the mean line of the wire which passes through the barycenters of the straight sections, in planes perpendicular to the preferred direction of the wire, is substantially rectilinear and is hereinafter called the axis of the wire. The diameter of the wire is defined here as being a quantity associated with the perimeter of the wire at the level of a cross section. It may be the diameter of a disc having the same surface as the cross section of the wire. The local diameter, also called the diameter below, is the diameter of the wire at a given height thereof along the axis of the wire. The diameter
    B16168 - Small medium pix is the mean, for example arithmetic, of the local diameters along the wire or a portion of it.
    Figure 1 is a partial and schematic sectional view of an optoelectronic device 10 made from wires as described above and adapted to the emission of electromagnetic radiation. According to one embodiment, an optoelectronic device 10 is provided comprising at least two integrated circuits 12 and 14, also called chips. The first integrated circuit 12 includes light emitting diodes. The second integrated circuit 14 comprises electronic components, in particular transistors, used for controlling the light-emitting diodes of the first integrated circuit 12. The first integrated circuit 12 is fixed to the second integrated circuit, for example by molecular bonding or by a type of connection FlipChip, in particular a Flip-Chip process using beads or microtubes. The first integrated circuit 12 is called the optoelectronic circuit or optoelectronic chip in the following description and the second integrated circuit 14 is called the control circuit or the control chip in the rest of the description.
    Preferably, the description optoelectronic chip.
    comprises only light-emitting diodes and elements for connecting these light-emitting diodes and the control chip comprises all of the electronic components necessary for controlling the optoelectronic chip.
    light emitting diodes of the
    Alternatively, the optoelectronic chip 12 may also include other electronic components in addition to the light emitting diodes.
    FIG. 1 represents, in the left part, the elements of the optoelectronic chip 12 for a display pixel, the structure being repeated for each display pixel, and in the right part, elements adjacent to the display pixels and which can be common to several display pixels.
    The optoelectronic chip 12 comprises, from bottom to top in FIG. 1:
    B16168 - Small pix an electrically insulating layer 16, at least partially transparent to electromagnetic radiation emitted by light-emitting diodes and which delimits a face 17;
    an electrically conductive layer 18, at least partially transparent to the electromagnetic radiation emitted by the light-emitting diodes;
    first wires 20 (three first wires being shown), of height H, and of diameter Dl, second wires 22 (three second wires being represented), of height H, and of diameter D2 and third wires 24 (three second wires being shown), of height H, and of diameter D3, the first, second and third wires being of axes parallel and perpendicular to the face 17, extending from the conductive layer 18 and in contact with the conductive layer 18, the diameter D1 being less than diameter D2 and diameter D2 being less than diameter D3;
    a first head 26 at the end of each first wire 20 opposite the conductive layer 18, a second head 28 at one end of each second wire 22 opposite the conductive layer 18 and a third head 30 at one end of each third wire 24 opposite the conductive layer 18;
    an electrically insulating layer 32 of a first electrically insulating material between the wires 20, 22, 24 having a thickness substantially equal to the sum of the height H and the dimension of the head 26 measured along the axis of the wires;
    an electrically insulating layer 34 of a second electrically insulating material, which may be different from the first insulating material or identical to the first insulating material, extending around the first insulating layer 32 and of the same thickness as the insulating layer 32;
    an opening 36 extending through the insulating layer 34 over the entire thickness of the insulating layer 34;
    an electrically conductive layer 38 being in the opening 36 and being in contact with the conductive layer 18;
    B16168 - Small pix of the disjoint portions 40 of an electrically conductive material on the insulating layer 32, the insulating layer 34, the conductive layer 38 and the parts of the heads 26, 28 and 30 projecting from the insulating layer 32 and in particular in contact with the parts of the heads 26, 28 and 30 projecting from the insulating layer 32;
    electrically conductive layers 42, 44, 46, 48 and separate, the conductive layer 42 being in contact with the first heads 26, the conductive layer 44 being in contact with the second heads 28, the conductive layer 46 being in contact with the third heads 30 and the conductive layer 48 being in contact with the conductive layer 38;
    an electrically insulating layer 50 covering the conductive layers 42, 44, 46 and 48 and extending between the conductive layers 42, 44, 46 and 48 and delimiting a face 51, preferably substantially planar; and electrically conductive pads 52, 54, 56, 58, which may have a multilayer structure, extending through the insulating layer 50 and flush with the face 51, the conductive pad 52 being in contact with the conductive layer 42, the conductive pad 54 being in contact with the conductive layer 44, the conductive pad 56 being in contact with the conductive layer 46 and the conductive pad 58 being in contact with the conductive layer 48.
    The control chip 14 comprises in particular on the side of the optoelectronic chip 12 an electrically insulating layer 60 delimiting a face 61, preferably substantially planar, and conductive pads 62 flush with the face 61, the conductive pads 62 being electrically connected to the conductive pads 52, 54, 56, 58. In the case where the control chip 14 is fixed to the optoelectronic chip 12 by molecular bonding, the conductive pads 62 can be in contact with the conductive pads 52, 54, 56, 58. In the case where the control chip 14 is fixed to the optoelectronic chip 12 by a flip chip type connection, solder balls or microtubes can be interposed
    B16168 - Small pix between the conductive pads 62 and the conductive pads 52, 54, 56, 58.
    FIGS. 2 to 8 are detailed views of embodiments of the head 26. The heads 28 and 30 may have a structure similar to the head 26.
    In FIG. 2, the head 26 comprises successively, moving away from the wire 20 along the axis Δ of the wire 20:
    a semiconductor portion 64 of the same material as the wire 20 and doped with a first type of conductivity, for example of type N;
    an active area 66; and a semiconductor portion 68 doped with a second type of conductivity, for example of the P type.
    A passivation layer, not shown, may be present on the lateral flanks of the active area 66 and of the semiconductor portions 64, 68.
    The assembly formed by each wire 20, 22, 24 and the associated head 26, 28, 30 constitutes an elementary light-emitting diode wired in axial configuration. The head 26, 28, 30 comprises in particular an active zone 66 which is the layer from which the majority of the electromagnetic radiation supplied by the light-emitting diode is emitted. According to one example, the active area 66 may include confinement means such as multiple quantum wells.
    The light-emitting diode is said to be in axial configuration insofar as the active area 66 essentially covers one face 65 of the semiconductor portion 64 substantially orthogonal to the axis Δ, and extends along the axis Δ. In addition, the semiconductor portion 68 essentially covers an upper face 67 of the active area 66 substantially orthogonal to the axis Δ, and extends along the axis Δ.
    In the embodiment shown in Figure 2, the cross section of the head 26 increases as one moves away from the wire 20 and the semiconductor portions 68 of adjacent light emitting diodes are distinct. According to a
    B16168 - Small pix Another embodiment, the semiconductor portions 68 of adjacent light emitting diodes can coalesce.
    Figure 3 is a view similar to Figure 2 of another embodiment in which the cross section of the head 26 is substantially constant.
    Figure 4 is a view similar to Figure 2 of another embodiment in which the cross section of the head 26 increases as one moves away from the wire 20 and then remains substantially constant, the area active 66 being located at the level of the section of constant section of the head 26.
    Figure 5 is a view similar to Figure 4 of another embodiment in which the cross section of the head 26 increases as one moves away from the wire 20 and then remains substantially constant, the area active 66 being located at the level of the section of increasing section of the head 26.
    Figure 6 is a view similar to Figure 2 of another embodiment in which the cross section of the head 26 is substantially constant for the semiconductor portion 64 and the active area 66 and increases for the semiconductor portion 68 as and as one moves away from the wire 20.
    According to one embodiment, each display pixel Pix comprises at least two types of light-emitting diodes. According to one embodiment, the light-emitting diodes of the first type, comprising for example the wires 20 and the heads 26, are adapted to emit a first radiation at a first wavelength and the light-emitting diodes of the second type, comprising for example the wires 22 and heads 28, are adapted to emit a second radiation at a second wavelength. According to one embodiment, each display pixel Pix comprises at least three types of light-emitting diodes, the light-emitting diodes of the third type, comprising for example the wires 24 and the heads 30, being adapted to emit a third radiation at a third length. wave. The first, second and third wavelengths can be different.
    B16168 - Small pix
    According to one embodiment, the first wavelength corresponds to blue light and is in the range of 430 nm to 490 nm. According to one embodiment, the second wavelength corresponds to green light and is in the range of 510 nm to 570 nm. According to one embodiment, the third wavelength corresponds to red light and is in the range of 600 nm to 720 nm.
    According to one embodiment, each display pixel Pix comprises light-emitting diodes of a fourth type, the light-emitting diodes of the fourth type being adapted to emit a fourth radiation at a fourth wavelength. The first, second, third and fourth wavelengths can be different. According to one embodiment, the fourth wavelength corresponds to yellow light and is in the range of 570 nm to 600 nm.
    For each display pixel, the elementary light-emitting diodes having wires of the same diameter are with common electrodes and when a voltage is applied between the conductive layer 18 and the conductive layer 42, 44 or 46, light radiation is emitted by the active areas of these elementary light emitting diodes.
    In the present embodiment, the electromagnetic radiation emitted by each light-emitting diode escapes from the optoelectronic device 12 through the face 17. Preferably, each conductive layer 42, 44, 46 is reflective and makes it possible, advantageously, to increase the proportion of the radiation emitted by the light-emitting diodes which escapes from the optoelectronic device 10 through the face 17.
    The optoelectronic chip 12 and the control chip 14 being stacked, the lateral dimensions of the optoelectronic device 10 are reduced. According to one embodiment, the lateral dimension of a display pixel, measured perpendicular to the axes of the wires is less than 5 μm, preferably less than 4 μm, for example approximately 3 μm. In addition, the optoelectronic chip 12 can have the same dimensions as
    B16168 - Small pix the control chip 14. As a result, the compactness of the optoelectronic device 10 can, advantageously, be increased.
    The conductive layer 18 is adapted to polarize the active areas of the heads 26, 28, 30 and to allow the electromagnetic radiation emitted by the light-emitting diodes to pass. The material forming the conductive layer 18 can be a transparent and conductive material such as graphene or a transparent and conductive oxide (or TCO, acronym for Transparent Conducting Oxide), in particular indium tin oxide (or ITO, acronym English for Indium Tin Oxide), zinc oxide doped or not with aluminum, or gallium or boron. By way of example, the conductive layer 18 has a thickness between 20 nm and 500 nm, preferably between 20 nm and 100 nm.
    The conductive layer 38, the conductive layers 42, 44, 46, 48 and the conductive pads 52, 54, 56, 58 may be made of metal, for example aluminum, silver, copper, gold or ruthenium or a alloy of at least two of these compounds. The conductive layer 38 can have a thickness of between 100 nm and 3 μm. The conductive layers 42, 44, 46, 48 can have a thickness of between 100 nm and 2 μm. The minimum lateral dimension, in a plane perpendicular to the face 17, is between 150 nm and 1 μm, for example approximately 0.25 μm. The conductive pads 52, 54, 56, 58 can have a thickness of between 0.5 μm and 2 μm.
    Each of the insulating layers 16, 32, 34 and 50 is made of a material chosen from the group comprising silicon oxide (SiOg), silicon nitride (Si x Ny, where x is approximately equal to 3 and y is approximately equal to 4, for example S13N4), silicon oxynitride (in particular of general formula SiO x Ny, for example SigONg), hafnium oxide (HfOg) or aluminum oxide (AlgOg). According to one embodiment, the insulating layer 74 is made of silicon oxide and the insulating layer 76 is made of silicon nitride. The thickness of each insulating layer 74, 76 is between 10 nm and 100 nm, preferably between 20 nm and 60 nm, in particular equal to approximately 40 nm. The insulating layer 16 can have a
    B16168 - Small pix maximum thickness between 100 nm and 5 pm. The insulating layers 32 and 34 can have a maximum thickness of between 0.5 μm and 2 μm. The insulating layer 50 can have a maximum thickness of between 0.5 μm and 2 μm.
    The conductive portions 40 are made of a material which is both a good electrical conductor and which has better contact resistance with the material making up the upper layer of the heads 26, 28, 30 than the material making up the conductive layers 42, 44, 46, 48. The conductive portions 40 are for example made of nickel (Ni). The conductive portions 40 can have a thickness of between 0.5 nm and 10 nm. The conductive portions 40 make it possible to obtain a weakly resistive contact between the heads 28, 28, 30 and the conductive layers 42, 44, 46.
    Each wire 20, 22, 24 and each semiconductor portion 64, 68 is, at least in part, formed from at least one semiconductor material. According to one embodiment, the semiconductor material is chosen from the group comprising compounds III-V, compounds II-VI or semiconductors or compounds of group IV.
    The wires 20, 22, 24 and the semiconductor portions 64, 68 can be, at least in part, formed from a first semiconductor material mainly comprising a compound III-V, for example a compound III-N, a compound II -VI or at least one element from group IV. Examples of group III elements include gallium (Ga), indium (In) or aluminum (Al). Examples of III-N compounds are GaN, AIN, InN, InGaN, AlGaN or AlInGaN. Other elements of group V can also be used, for example, phosphorus or arsenic. Generally, the elements in compound III-V can be combined with different molar fractions. Examples of group II elements include group IIA elements, including beryllium (Be) and magnesium (Mg) and group IIB elements, including zinc (Zn), cadmium (Cd) and mercury ( Hg). Examples of Group VI items include items from
    B16168 - Small pix group VIA, in particular oxygen (O) and tellurium (Te). Examples of compounds II-VI are ZnO, ZnMgO, CdZnO, CdZnMgO, CdHgTe, CdTe or HgTe. Generally, the elements in compound II-VI can be combined with different molar fractions. Examples of group IV semiconductor materials are silicon (Si), carbon (C), germanium (Ge), silicon carbide alloys (SiC), silicon germanium alloys (SiGe) or germanium carbide alloys (GIC). The semiconductor material of the wires 20, 22, 24 and / or of the semiconductor portions 64, 68 may comprise a dopant, for example silicon ensuring an N-type doping of a III-N compound, or magnesium ensuring a type doping P of a III-N compound.
    Each wire 20, 22, 24 may have a semiconductor structure elongated along an axis substantially perpendicular to the face 17. Each wire 20, 22, 24 may have a generally cylindrical shape. The axes of two adjacent wires 20, 22, 24 can be spaced from 100 nm to 3 pm and preferably from 200 nm to 1.5 pm. The height H of each wire 20, 22, 24 can be between 150 nm and 10 pm, preferably between 200 nm and 1 pm, more preferably between 250 nm and 750 nm. The
    average diameter of each wire 20 22, 24 can be between 50 nm and 10 pm, preferably Between 100 nm and 2 pm, more preferably between 120 nm and 1 pm. The right section of the son 20 22, 24 can to have
    different shapes, such as, for example, an oval, circular or polygonal shape, in particular triangular, rectangular, square or hexagonal.
    The active area 66 may comprise at least one quantum well, comprising a layer of a second semiconductor material having a band gap energy lower than that of the semiconductor portion 64 and of the semiconductor portion 68, preferably interposed between two barrier layers, thus improving the containment of charge carriers. The second semiconductor material can comprise compound III-V, II-VI or IV of the doped semiconductor portions 64, 68
    B16168 - Small pix in which at least one additional element is incorporated. For example, in the case of a wire 20, 22, 24 made from GaN, the second material forming the quantum well is preferably InGaN. The atomic percentage of the additional element depends on the desired optical properties and on the emission spectrum of the wire. The active area 66 may be formed of a single quantum well or of several quantum wells.
    According to a preferred embodiment, each wire 20, 22, 24 is produced based on GaN, the quantum well (s) of the active area 66 being produced in InGaN. The emission wavelength of the active zone 66 depends in particular on the proportion of indium in the quantum well (s). The semiconductor portion 64 may be formed of GaN, and be doped with the first type of conductivity, for example of the N type, in particular with silicon. The height of the semiconductor portion 64, measured along the Δ axis, can be between 10 nm and 1 pm, for example between 20 nm and 200 nm. The active area 66 may include one or more quantum wells, for example made of InGaN.
    The active area 66 may comprise a single quantum well which extends continuously along the axis Δ between the semiconductor portions 64,
    68. Alternatively, it may comprise multiple quantum wells and is then formed of an alternation, along the axis Δ, of quantum wells produced for example in InGaN, and of barrier layers produced for example in GaN. The height of the active area 66, measured along the axis Δ, can be between 10 nm and 500 nm, for example between 20 nm and 100 nm. The semiconductor portion 68 may be formed of GaN, and be doped with the second type of conductivity opposite to the first, for example of the P type, in particular by magnesium. The height of the semiconductor portion 68 can be between 50 nm and 5 pm, for example between 100 nm and 1 pm. The semiconductor portion 68 may include an electron blocking layer located at the interface with the active area
    66. The electron blocking layer may be formed from a compound
    B16168 - Small ternary pix III-N, for example AlGaN or AUnN, advantageously doped P. It makes it possible to increase the rate of radiative recombinations within the active zone 66.
    In the embodiments shown in Figures 2 to 7, the layers forming the active area 66 are stacked along the axis Δ.
    Figure 7 is a view similar to Figure 4 of another embodiment in which the active area 66 comprises a central portion Lg of a semiconductor material having a first forbidden band and a peripheral portion Bg disposed other than the central portion along the axis Δ and in contact with the central portion, the peripheral portion being made of a semiconductor material having a second prohibited band greater than the first prohibited band.
    FIGS. 8A to 8Q are partial and schematic sectional views of the structures obtained in successive stages of an embodiment of a method for manufacturing the optoelectronic device 10 shown in FIG. 1.
    FIG. 8A represents the structure obtained after the following steps:
    forming a support 70 corresponds to the stacking, from bottom to top in FIG. 8A, of a substrate 71, at least one nucleation layer, also called germination layer, two nucleation layers 72 and 73 being shown at by way of example in FIG. 8A, an electrically insulating layer 74 and an electrically insulating layer 76 on the insulating layer 74, the insulating layers 74, 76 being made of different materials;
    forming first openings 78 in the insulating layers 74 and 76 to expose parts of the nucleation layer 73 at the desired locations of the first wires 20, the diameter of the first openings 78 substantially corresponding to the diameter of the first wires 20, of the second openings 80 in insulating layers 74 and 76 to expose portions of the nucleation layer 73 at the desired locations of the second
    B16168 - Small pix wires 22, the diameter of the second openings 80 corresponding substantially to the diameter of the second wires 22, and of the third openings 82 in the insulating layers 74 and 76 to expose parts of the nucleation layer 73 at the desired locations of the third wires 24, the diameter of the third openings 82 corresponding substantially to the diameter of the third wires 24; and simultaneously growing the wires 20, 22, 24 from the nucleation layer 72 in the openings 78, 80, 82.
    Alternatively, the insulating layers 74, 76 can be replaced by a single insulating layer.
    The substrate 71 may correspond to a one-piece structure or correspond to a layer covering a support made of another material. The substrate 71 is preferably a semiconductor substrate, for example a silicon, germanium, silicon carbide substrate, a III-V compound, such as GaN or GaAs, or a ZnO substrate, or a conductive substrate. , for example a substrate made of a metal or a metal alloy, in particular copper, titanium, molybdenum, a nickel-based alloy and steel. Preferably, the substrate 71 is a monocrystalline silicon substrate. Preferably, it is a semiconductor substrate compatible with the manufacturing methods used in microelectronics. The substrate 71 can correspond to a multilayer structure of the silicon on insulator type, also called SOI (English acronym for Silicon On Insulator). The substrate 71 can be highly doped, lightly doped or undoped.
    The nucleation layers 72, 73 are made of a material which promotes the growth of the wires 20, 22, 24. The material making up each nucleation layer 72, 73 can be a metal, a metal oxide, a nitride, a carbide or a boride of a transition metal of column IV, V or VI of the periodic table of the elements or a combination of these compounds and preferably a nitride of a transition metal of column IV, V or VI of the periodic table of the elements or a combination of these
    B16168 - Small pix composed. For example, each germination layer 72, 73 can be made of aluminum nitride (AIN), aluminum oxide (AI2O3), boron (B), boron nitride (BN), titanium ( Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), hafnium (Hf), hafnium nitride (HfN), niobium (Nb), niobium nitride (NbN), zirconium (Zr), zirconium borate (ZrB2), zirconium nitride (ZrN), silicon carbide (SiC), nitride and tantalum carbide (TaCN), or magnesium nitride under the form Mg x Ny, where x is approximately equal to 3 and y is approximately equal to 2, for example magnesium nitride according to the form MggNg. Each nucleation layer 72, 73 has, for example, a thickness between 1 nm and 100 nm, preferably between 10 nm and 30 nm.
    Each of the insulating layers 74 and 76 is made of a material chosen from the group comprising silicon oxide (SiOg), silicon nitride (Si x Ny, where x is approximately equal to 3 and y is approximately equal to 4, for example S13N4), silicon oxynitride (in particular of general formula SiO x Ny, for example SigONg), hafnium oxide (HfOg) or aluminum oxide (AI2O3). According to one embodiment, the insulating layer 74 is made of silicon oxide and the insulating layer 76 is made of silicon nitride. The thickness of each insulating layer 74, 76 is between 10 nm and 100 nm, preferably between 20 nm and 60 nm, in particular equal to approximately 40 nm.
    The process for growing the wires 20, 22, 24 can be a chemical vapor deposition (CVD) or organometallic chemical vapor deposition (MOCVD, acronym for MetalOrganic Chemical Vapor Deposition) type. , also known as organometallic vapor phase epitaxy (or MOVPE, English acronym for Metal-Organic Vapor Phase Epitaxy). However, processes such as molecular beam epitaxy (MBE, acronym for Molecular-Beam Epitaxy), gas source MBE (GSMBE), organometallic MBE (MOMBE), plasma-assisted MBE (PAMBE), atomic layer epitaxy (ALE, acronym
    B16168 - Small English pix for Atomic Layer Epitaxy) or hydride vapor epitaxy (HVPE, acronym for Hydride Vapor Phase Epitaxy) can be used. In addition, electrochemical processes can also be used, for example, chemical bath deposition (CBD), hydrothermal processes (also called hydrothermal processes), liquid aerosol pyrolysis or electrodeposition .
    By way of example, the process can comprise the injection into a reactor of a precursor of a group III element and of a precursor of a group V element. Examples of precursors of group III elements are trimethylgallium (TMGa), triethylgallium (TEGa), trimethylindium (TMIn) or trimethylaluminum (TMA1). Examples of group V element precursors are ammonia (NH3), tertiarybutylphoshine (TBT), arsine (ASH3) or dimethylhydrazine (UDMH).
    The height of each wire 20, 22, 24 at the end of the growth step can be between 250 nm and 15 pm, preferably between 500 nm and 5 pm, more preferably between 1 pm and 3 pm. The height of the first wires 20 is different from the height of the second wires 24 and the height of the third wires 24. The height of the wires 20, 22, 24 depends in particular on the diameter of the wire and on the distance between the wires. According to one embodiment, the height of the first wires 20 is greater than the height of the second wires 22 and the height of the second wires 22 is greater than the height of the third wires 24.
    Each nucleation layer 72, 73 and each insulating layer 74, 76 can be deposited by way of example by chemical vapor deposition assisted by plasma (PECVD, acronym for Plasma-Enhanced Chemical Vapor Deposition), chemical deposition in phase low pressure vapor (LPCVD, acronym for LowPressure Chemical Vapor Deposition), chemical vapor deposition at atmospheric pressure (SACVD, acronym for Sub-Atmospheric Chemical Vapor Deposition), CVD, physical deposition
    B16168 - Small pix in vapor phase (PVD, acronym for Physical Vapor Deposition), or atomic layer deposition (ALD, acronym for Atomic Layer Deposition).
    FIG. 8B represents the structure obtained after having deposited a dielectric layer 83 on all of the wires 20, 22, 24 and on the insulating layer 76 between the wires 20, 22, 24.
    The dielectric layer 83 be of the same material as the insulating layer 74, that is to say in a material different from the insulating layer 76. According to one embodiment, the minimum thickness of the layer 83 is greater than the height of the smallest wires 20, 22, 24. Preferably, the minimum thickness of the layer 83 is greater than the height of the largest wires 20, 22, 24.
    By way of example, the thickness of the dielectric layer 83 is between 250 nm and 15 μm, preferably between 300 nm and 5 μm, for example equal to approximately 2 μm. The insulating layer 83 can be formed by the same methods as those used for the formation of the insulating layers 72, 74.
    FIG. 8C represents the structure obtained after having thinned and planarized the insulating layer 83 and part of the wires 20, 22, 24 to delimit a planar face 84 at a height of the germination layer 76 for example between 150 nm and 10 μm . The etching is for example a mechanochemical planarization or CMP (English acronym for Chemical-Mechanical planarization). The presence of the insulating layer 83 between the wires 20, 22, 24 makes it possible to implement an etching process of the CMP type, which would be difficult, if not impossible, if only the wires were present. After this step, all the wires 20, 22, 24 have the same height. The etching of the insulating layer 83 and of part of the wires 20, 22, 24 can be carried out in several stages. Alternatively, the step of thinning and planarizing the insulating layer 83 and part of the wires 20, 22, 24 may not be present when the wires 20, 22, 24 have substantially the same height.
    B16168 - Small pix
    FIG. 8D represents the structure obtained after having completely removed the dielectric layer 83 to expose the insulating layer 76 and the wires 20, 22, 24. The insulating layer 76 can then play the role of stop layer during the etching of layer dielectric 83. The dielectric layer 83 can be removed by wet etching. As a variant, the etching of the dielectric layer 83 may be only partial, a residual layer being preserved on the insulating layer 76.
    FIG. 8E represents the structure obtained after the simultaneous formation of the heads 26, 28, 30 for each wire 20, 22,
    24. The successive layers forming the heads can be produced by the same methods as those described for the formation of the wires 20, 22, 24. Such methods are described in the publication by Katsumi Kishino et al entitled Monolithic Integration of InGaN-Based Nanocolumn Light-Emitting Diodes with Different Emision Colors (2013, The Japan Society of Applied Physics, Applied Physics Express 6 (2013) 012101) and the publication of Yong-Ho Ra entitled Full-Color Single Nanowire Pixels for Projection Displays.
    The formation of the active zones of the heads 26, 28, 30 may comprise, in addition to the injection into the reactor of a precursor of a group III element and of a precursor of a group V element, a precursor an additional element, in particular indium. The incorporation rate of the additional element in the active area 66 depends in particular on the lateral dimensions of the active areas, the distance between the wires 20, 22, 24, the height of the active areas with respect to the upper surface of the dielectric layer 83 (if it is not completely etched) or else of the insulating layer 76 (if the dielectric layer 83 is completely etched). Different indium incorporation rates are thus obtained for the active areas of the heads 26, 28, 30, although they are formed simultaneously. In operation, the heads 26, 28, 30 are then
    B16168 - Small pix suitable for emitting electromagnetic radiation at different wavelengths.
    If the dielectric layer 83 were maintained between the wires 20, 22, 24, the methods implemented for the formation of the heads 26, 28, 30 could also lead to the formation of undesirable crystals on the dielectric layer 83. The at least partial removal of the dielectric layer 83 means that there is little formation of parasitic crystals on the side walls of the wires and at the foot of the wires, in particular due to the screen effect due to all of the wires.
    FIG. 8F represents the structure obtained after the following steps:
    forming the insulating layer 32;
    forming the insulating layer 34; and etching or thinning the insulating layer 34 over part of its thickness to define a substantially planar face 86.
    The insulating layer 32 can be produced by conformal deposition, for example by LPCVD. The process for forming the insulating layer 32 is preferably carried out at a temperature below 700 ° C. so as not to damage the active areas of the light-emitting diodes. In addition, a method of the LPCVD type makes it possible to obtain good filling between the wires 20, 22, 24. The thickness deposited of the insulating layer 32 can be between 50 nm and 500 nm, for example around 150 nm. The insulating layer 34 can be produced by conformal deposition, for example by PECVD. The deposited thickness of the insulating layer 34 can be greater than or equal to 2 μm. The partial etching of the insulating layer 34 can be carried out by CMP. The etching can be stopped in the insulating layer 34, as shown in FIG. 8F, in the insulating layer 32 but in any case before exposing the heads 26, 28, 30.
    FIG. 8G represents the structure obtained after having etched the insulating layers 32, 34 until exposing the upper surfaces of the heads 26, 28, 30. The etching is for example a
    B16168 - Small pix etching of the reactive ion etching type (RIE, acronym for Reactive-Ion Etching) or an inductively coupled plasma etching (ICP, acronym for Inductively Coupled Plasma). The heads 26, 28, 30 may not have the same dimensions, some heads 26, 28, 30 may be more exposed than others. The heads 26, 28, 30 are not engraved at this stage. The etching is preferably an anisotropic etching. Unrepresented portions of the layer 32 can be kept on the side walls of the heads 26, 28, 30. The layer located at the top of the heads 26, 28, 30 acts as an etching stop layer. According to one embodiment, during the formation of the heads 26, 28, 30, an additional layer is added to the tops of the heads 26, 28, 30 to act as an etching stop layer. It can be a layer of AIN.
    FIG. 8H represents the structure obtained after the following steps:
    when etching stop layers are present on the heads 26, 28, 30, removal of the etch stop layers; and forming the metal portions 40 on the exposed parts of the heads 26, 28, 30, on the insulating layer 32 and on the insulating layer 34.
    When the etching stop layers on the heads 26, 28, 30 are made of AIN, they can be removed by etching of the tetramethylammonium hydroxide (TMAH) type. The formation of the metal portions 40 may successively comprise the deposition of a metallic layer 1 nm thick, for example nickel, and a thermal annealing step, for example at a temperature of 550 ° C., which leads to the formation of the disjoint portions 40.
    Figure 81 shows the structure obtained after the following steps:
    depositing a metal layer on the structure shown in FIG. 8H, for example by sputtering, for example having a thickness of 0.5 μm;
    B16168 - Small pix etching of the layer to delimit the conductive layers 42, 44, 46, 48.
    FIG. 8J represents the structure obtained after the following steps:
    depositing the insulating layer 50 on the structure shown in FIG. 81; and forming the conductive pads 52, 54, 56, 58, for example of copper.
    FIG. 8K represents the structure obtained after having fixed the control chip 14 to the optoelectronic chip 12. The fixing of the control chip 14 to the optoelectronic chip 12 can be carried out using inserts such as connection microbeads, not shown . Alternatively, the control chip 14 can be attached to the optoelectronic chip by direct bonding, without the use of inserts. Direct bonding can comprise a direct metal-to-metal bonding of metal zones, in particular the conductive pads 62 of the control chip 14 and of metal zones, in particular the conductive pads 52, 54, 56, 58, of the optoelectronic chip 12 and a dielectric-dielectric bonding of dielectric zones, in particular the insulating layer 50, of the control chip 14, and of dielectric zones, in particular the insulating layer 50, of the optoelectronic chip 12. The fixing of the control chip 14 to the optoelectronic chip 12 can be achieved by a thermocompression process in which the optoelectronic chip 12 is pressed against the control chip 14, with the application of pressure and heating.
    FIG. 8L represents the structure obtained after removing the substrate 71 and the germination layers 72, 73. The removal of the substrate 71 can be carried out by grinding and / or wet etching. The removal of the germination layers 72, 73 can be carried out by wet etching, dry etching or by CMP. The insulating layer 74 or 76 can act as an etching stop layer during the etching of the germination layer 73.
    B16168 - Small pix
    FIG. 8M represents the structure obtained after having etched the insulating layers 74 and 76, after having partially etched the insulating layer 32, the insulating layer 34 and the wires 20, 22, 24 to delimit a substantially flat face 88. This removal step can be carried out by CMP. The remaining height of the wires 20, 22, 24 is equal to the height H, for example around 0.5 μm.
    FIG. 8N represents the structure obtained after having formed the conductive layer 18 on the face 88, for example by depositing a layer of TCO on the entire face 88, for example having a thickness of 50 nm, and by etching this layer by photolithography techniques to keep only the TCO 18 layer.
    FIG. 80 represents the structure obtained after having etched the opening 36 in the insulating layer 34 over the entire thickness of the insulating layer 34 to expose the conductive layer 48. This can be achieved by photolithography techniques.
    FIG. 8P represents the structure obtained after having formed the conductive layer 38 in the opening 36 and on the face 88 in contact with the conductive layer 18. This can be achieved by depositing a stack of conductive layers, for example of the Ti / TiN / AlCu, over the entire structure on the side of the face 88, and by etching this layer by photolithography techniques so as to retain only the conductive layer 38.
    FIG. 8Q represents the structure obtained after having formed the insulating layer on the conductive layer 18 delimiting the face 17. It is for example a layer of SiON deposited by PECVD with a thickness of 1 μm.
    An additional step of forming reliefs on the face 17, also called the texturing step, can be provided to increase the extraction of light.
    According to another embodiment of a method for manufacturing the optoelectronic device, the heads 26, 28, 30 are not formed simultaneously on all of the wires 20, 22,
    B16168 - Small pix
    24, but sequentially, with three stages of growth during which the threads at the top of which heads should not be formed are masked. The wires 20, 22, 24 can then all have the same diameter and the same interfil pitch, the 5 active zones being formed with different properties, for example with different proportions of indium, to obtain emissions at lengths of different wave.
    Particular embodiments have just been described. Different variants and modifications will appear to those skilled in the art. Three-dimensional semiconductor structures have been described which are adapted to emit light radiation from an electrical signal, thus forming light-emitting diodes. Alternatively, the structures can be adapted to detect incident light radiation and to produce an electrical signal in response, thereby forming a photodiode. Applications can relate to the field of optoelectronics or photovoltaics.
    B16168 - Small pix
    权利要求:
    Claims (14)
    [1" id="c-fr-0001]
    1. Optoelectronic device (10) comprising a first optoelectronic circuit (12) fixed to a second electronic circuit (14), the second electronic circuit (14) comprising electrically conductive pads (62), the first optoelectronic circuit comprising pixels and comprising , for each pixel:
    a first electrically conductive layer (18);
    at least first and second three-dimensional semiconductor elements (20, 22) extending
    perpendicularly at the first layer conductive electrically and at contact of the first conductive layer electrically and having the same height (H) measured perpendicularly electrically; at the first layer conductive
    first active areas (66) resting on the ends of the first three-dimensional semiconductor elements opposite to the first electrically conductive layer and adapted to emit or pick up a first electromagnetic radiation at a first wavelength;
    second active zones (66) resting on the ends of the second three-dimensional semiconductor elements opposite to the first electrically conductive layer and adapted to emit or receive a second electromagnetic radiation at a second wavelength different from the first wavelength; and second, third and fourth electrically conductive layers (42, 44, 48) electrically connected to the electrically conductive pads (62), the second electrically conductive layer being connected to the first active areas, the third electrically conductive layer (44) being connected to the second active areas and the fourth electrically conductive layer (48) being connected to the first electrically conductive layer.
    B16168 - Small pix
    [2" id="c-fr-0002]
    2. Optoelectronic device according to claim 1, in which the diameter (D1) of each first semiconductor element in contact with the first electrically conductive layer is less than the diameter (D2) of each second semiconductor element in contact with the first electrically conductive layer.
    [3" id="c-fr-0003]
    3. Optoelectronic device according to claim 1 or 2, in which the first three-dimensional semiconductor elements are regularly distributed in a first average pitch and in which the second three-dimensional semiconductor elements are regularly distributed in a second average pitch different from the first average pitch.
    [4" id="c-fr-0004]
    4. Optoelectronic device according to any one of claims 1 to 3, in which the first optoelectronic circuit (12) further comprises, for each pixel:
    at least third three-dimensional semiconductor elements (24) extending perpendicular to the first electrically conductive layer (18) and in contact with the first electrically conductive layer, the first, second and third three-dimensional semiconductor elements (20, 22, 24) having the same height (H) measured perpendicular to the first electrically conductive layer;
    third active areas (66) resting on the ends of the third three-dimensional semiconductor elements opposite to the first electrically conductive layer and adapted to emit or pick up electromagnetic radiation at a third wavelength different from the first and second wavelengths; and a fifth electrically conductive layer (46) electrically connected to one of the electrically conductive pads (62) and connected to the third active areas.
    [5" id="c-fr-0005]
    5. Optoelectronic device according to claim 4, in which the diameter (D2) of each second semiconductor element in contact with the first electrically conductive layer is less than the diameter (D3) of each third
    B16168 - Small pix semiconductor element in contact with the first electrically conductive layer.
    [6" id="c-fr-0006]
    6. Optoelectronic device according to claim 4 or 5, wherein the third three-dimensional semiconductor elements are regularly distributed according to a third average pitch different from the first average pitch and from the second average pitch.
    [7" id="c-fr-0007]
    7. Optoelectronic device according to any one of claims 1 to 6, in which the first and second active zones (66) comprise a single quantum well or multiple quantum wells.
    [8" id="c-fr-0008]
    8. Optoelectronic device according to any one of claims 1 to 7, in which the first and second three-dimensional semiconductor elements (20, 22) are predominantly made of a semiconductor material chosen from the group comprising compounds III-V, compounds II- VI or the semiconductors or compounds of group IV.
    [9" id="c-fr-0009]
    9. Optoelectronic device according to any one of claims 1 to 8, in which the first and second three-dimensional semiconductor elements (20, 22) are of wire, conical or frustoconical shape.
    [10" id="c-fr-0010]
    10. Optoelectronic device according to any one of claims 1 to 9, in which the maximum dimension of each pixel measured parallel to the first electrically conductive layer (18) is less than 5 μm.
    [11" id="c-fr-0011]
    11. Method for manufacturing the optoelectronic device (10) according to any one of claims 1 to 10, comprising the following successive steps:
    a) forming the first optoelectronic circuit (12); and
    b) fixing the first optoelectronic circuit to a second electronic circuit (14) by electrically connecting the second, third and fourth electrically conductive layers (42, 44, 48) to the electrically conductive pads (62).
    [12" id="c-fr-0012]
    12. The method as claimed in claim 11, in which step a) comprises the following successive steps:
    B16168 - Small pix
    c) simultaneously forming on a support (70) the first and second three-dimensional semiconductor elements (20, 22);
    d) simultaneously forming the first active areas (66) on the ends of the first three-dimensional semiconductor elements opposite the support and the second active areas (66) on the ends of the second three-dimensional semiconductor elements opposite the support;
    e) forming the second, third and fourth electrically conductive layers (42, 44, 48);
    f) remove the support; and
    g) forming the first electrically conductive layer (18).
    [13" id="c-fr-0013]
    13. The method of claim 12, wherein step a) comprises the following steps between steps c) and
    d):
    h) forming an electrically insulating layer (32) between the first three-dimensional semiconductor elements (20) and between the second three-dimensional semiconductor elements (22);
    i) partially etching the electrically insulating layer (32) and the first and second three-dimensional semiconductor elements so that the first and second three-dimensional semiconductor elements have the same height (H).
    [14" id="c-fr-0014]
    14. The method of claim 13, further comprising, between steps f) and g), the step of etching the electrically insulating layer (32) and the first and second three-dimensional semiconductor elements (20, 22) on the side opposite the first and second active areas (66).
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    同族专利:
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    CN111033747A|2020-04-17|
    US11195878B2|2021-12-07|
    TW201911558A|2019-03-16|
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    EP3646383A1|2020-05-06|
    JP2020527852A|2020-09-10|
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    法律状态:
    2019-01-04| PLSC| Publication of the preliminary search report|Effective date: 20190104 |
    2019-06-21| PLFP| Fee payment|Year of fee payment: 3 |
    2020-06-29| PLFP| Fee payment|Year of fee payment: 4 |
    2021-06-29| PLFP| Fee payment|Year of fee payment: 5 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1756161|2017-06-30|
    FR1756161A|FR3068517B1|2017-06-30|2017-06-30|OPTOELECTRONIC DEVICE COMPRISING THREE DIMENSIONAL SEMICONDUCTOR STRUCTURES IN AXIAL CONFIGURATION|FR1756161A| FR3068517B1|2017-06-30|2017-06-30|OPTOELECTRONIC DEVICE COMPRISING THREE DIMENSIONAL SEMICONDUCTOR STRUCTURES IN AXIAL CONFIGURATION|
    JP2019572565A| JP2020527852A|2017-06-30|2018-06-28|Optoelectronic device with three-dimensional semiconductor structure with axial configuration|
    KR1020207001573A| KR20200019215A|2017-06-30|2018-06-28|Optoelectronic device with axial array of three-dimensional semiconductor structure|
    PCT/FR2018/051604| WO2019002786A1|2017-06-30|2018-06-28|Optoelectronic device comprising three-dimensional semiconductor structures in an axial configuration|
    US16/626,510| US11195878B2|2017-06-30|2018-06-28|Optoelectronic device comprising three-dimensional semiconductor structures in an axial configuration|
    CN201880055485.0A| CN111033747A|2017-06-30|2018-06-28|Optoelectronic device comprising a three-dimensional semiconductor structure arranged in an axial direction|
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    TW107122484A| TW201911558A|2017-06-30|2018-06-29|Photoelectric device including a three-dimensional semiconductor structure arranged in an axial direction|
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